Measurement of the Higgs mass via the channel : e+e- -> ZH -> e+e- + X

In this communication, the mass declined for the decay channel, e+e- -> ZH -> e+e- + X, as measured by the ILD detector was studied. The Higgs mass is assumed to be 120 GeV and the center of mass energy is 250 GeV. For an integrated luminosity of 250 fb-1, the accuracy of the reconstruction and the good knowledge of the initial state allow for the measurement of the Higgs boson mass with a precision of about 100 MeV.Comment: 7 pages, 14 figures, LCWS/ILC 2010 (International Linear Collider Workshop 2010 LCWS10 and ILC10

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout

The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000)

Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design

A very low power and low signal 5 bit 50 M samples/s double sampling pipelined ADC for Monolithic Active Pixel Sensors in high energy physics and biomedical imaging applications

International audienc

Electronic tests of the barrel presampler mother boards

The electrical characteristics of the barrel presampler mother boards are recalled. The results of the tests of the first full-size mother board are presented. They satisfy our specifications

Electrical tests of e. m. barrel presampler sectors

A description of the tests and electronics used to control the presampler sectors, before and after their assembly, is given. An example of the results obtained for the first two sectors, tested at room and liquid nitrogen temperatures, is shown

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

soumis à JINSTA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1µs. The size for the layout is 80µm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20µm wide

Formula for proton-nucleus reaction cross section at intermediate energies and its application

We construct a formula for proton-nucleus total reaction cross section as a function of the mass and neutron excess of the target nucleus and the proton incident energy. We deduce the dependence of the cross section on the mass number and the proton incident energy from a simple argument involving the proton optical depth within the framework of a black sphere approximation of nuclei, while we describe the neutron excess dependence by introducing the density derivative of the symmetry energy, L, on the basis of a radius formula constructed from macroscopic nuclear models. We find that the cross section formula can reproduce the energy dependence of the cross section measured for stable nuclei without introducing any adjustable energy dependent parameter. We finally discuss whether or not the reaction cross section is affected by an extremely low density tail of the neutron distribution for halo nuclei.Comment: 7 pages, 4 figures, added reference

Shower development of particles with momenta from 15 GeV to 150 GeV in the CALICE scintillator-tungsten hadronic calorimeter

We present a study of showers initiated by electrons, pions, kaons, and protons with momenta from 15 GeV to 150 GeV in the highly granular CALICE scintillator-tungsten analogue hadronic calorimeter. The data were recorded at the CERN Super Proton Synchrotron in 2011. The analysis includes measurements of the calorimeter response to each particle type as well as measurements of the energy resolution and studies of the longitudinal and radial shower development for selected particles. The results are compared to Geant4 simulations (version 9.6.p02). In the study of the energy resolution we include previously published data with beam momenta from 1 GeV to 10 GeV recorded at the CERN Proton Synchrotron in 2010.Comment: 35 pages, 21 figures, 8 table